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1 of 13 rev: 121203 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description the DS1337 serial real-time clock is a low-power clock/calendar with two programmable time-of-day alarms and a programmable square-wave output. address and data are transferred serially through a 2-wire, bidirectional bus. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24-hour or 12-hour format with am/pm indicator. applications handhelds (gps, pos terminal, mp3 player) consumer electronics (set-top box, vcr/digital recording) office equipment (fax/printer, copier) medical (glucometer, medicine dispenser) telecommunications (router, switcher, server) other (utility meter, vending machine, thermostat, modem) features real-time clock (rtc) counts seconds, minutes, hours, day, date, month, and year with leap-year compensation valid up to 2100 two-wire serial interface two time-of-day alarms oscillator stop flag programmable square-wave output defaults to 32khz on power-up available in 8-pin dip, so, or sop ordering information part temp range pin-package top mark DS1337 -40c to +85c 8 dip (300 mil) DS1337 DS1337s -40c to +85c 8 so (150 mil) DS1337 DS1337u -40c to +85c 8 sop 1337 pin configurations DS1337 serial real-time clock www.maxim-ic.com typical operating circuit dip inta top view x1 x2 gnd v cc scl sda sqw / int b DS1337 so , sop x1 x2 gnd v cc scl sda sqw / int b int a DS1337
DS1337 serial real-time clock 2 of 13 absolute maximum ratings voltage range on any pin relative to ground -0.3v to +6.0v operating temperature range -40c to +85c storage temperature range -55c to +125c soldering temperature range see ipc/jedec j-std-020a specification stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect device. recommended dc operating conditions (t a = -40c to +85c) parameter symbol conditions min typ max units supply voltage v cc 1.8 5.5 v oscillator voltage v osc 1.3 5.5 v scl, sda 0.7 x v cc v cc + 0.3 logic 1 v ih inta , sqw/ intb 5.5 v logic 0 v il -0.3 0.3 x v cc v dc electrical characteristics (v cc = 1.8v to 5.5v, t a = -40c to +85c.) parameter symbol conditions min typ max units input leakage i li (note 1) 1 a i/o leakage i lo (note 2) 1 a logic 0 output (v ol = 0.4v) i ol (note 2) 3 ma active supply current i cca (note 3) 150 a standby current i ccs (notes 4, 5) 1.5 a dc electrical characteristics ( v cc = 1.3v to 1.8v , t a = -40c to +85c.) parameter symbol conditions min typ max units timekeeping current (oscillator enabled) i osc (notes 4, 6, 7) 600 na data retention current (oscillator disabled) i ddr (note 4) 50 na crystal specifications* parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 45 k load capacitance c l 6 pf *the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations for dallas real-time clocks for additional specifications.
DS1337 serial real-time clock 3 of 13 ac electrical characteristics (v cc = 1.8v to 5.5v, t a = -40c to +85c.) parameter symbol conditions min typ max units fast mode 100 400 scl clock frequency f scl standard mode 100 khz fast mode 1.3 bus free time between a stop and start condition t buf standard mode 4.7 s fast mode 0.6 hold time (repeated) start condition (note 8) t hd:sta standard mode 4.0 s fast mode 1.3 low period of scl clock t low standard mode 4.7 s fast mode 0.6 high period of scl clock t high standard mode 4.0 s fast mode 0.6 setup time for a repeated start condition t su:sta standard mode 4.7 s fast mode 0 0.9 data hold time (notes 9, 10) t hd:dat standard mode 0 s fast mode 100 data setup time (note 11) t su:dat standard mode 250 ns fast mode 300 rise time of both sda and scl signals (note 12) t r standard mode 20 + 0.1c b 1000 ns fast mode 300 fall time of both sda and scl signals (note 12) t f standard mode 20 + 0.1c b 300 ns fast mode 0.6 setup time for stop condition t su:sto standard mode 4.0 s capacitive load for each bus line c b (note 12) 400 pf i/o capacitance c i/o 10 pf note 1: scl only. note 2: sda, inta , and sqw/ intb . note 3: i cca ?scl clocking at max frequency = 400khz, v il = 0.0v, v ih = v cc. note 4: specified with 2-wire bus inactive, v il = 0.0v, v ih = v cc. note 5: sqw enabled. note 6: specified with the sqw function disabled by setting intcn = 1. note 7: using recommended crystal on x1 and x2. note 8: after this period, the first clock pulse is generated. note 9 : a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ihmin of the scl signal) in order to bridge the undefined region of the falling edge of scl. note 10 : the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 11: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat to 250ns must then be met. this is automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the lo w period of the scl signal, it must output the next data bit to the sda line t r max + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 12: c b ?total capacitance of one bus line in pf.
DS1337 serial real-time clock 4 of 13 typical operating characteristics oscillator frequency vs. v cc DS1337 toc05 v backup (v) frequency (hz) 4.3 3.8 3.3 2.8 2.3 1.8 32767.50 32767.55 32767.60 32767.65 32767.70 32767.75 32767.45 1.3 4.8 v cc = 0v i osc vs. temperature (square-wave off) DS1337 toc03 temperature ( c) supply current (na) 80 60 40 20 0 -20 375 425 450 475 350 -40 v cc = 3.0v i cca vs. v cc (square-wave on) DS1337 toc04 v cc (v) supply current ( m a) 4.8 4.3 3.3 3.8 2.8 2.3 20 40 60 0 1.8 5.3 DS1337 toc02 400 450 500 550 600 650 700 750 800 850 350 i osc vs. v cc (square-wave on) v cc (v) supply current (na) 4.8 4.3 3.8 3.3 2.3 1.8 1.3 i osc vs. v cc (square-wave off) DS1337 toc01 v cc (v) supply current (na) 4.8 4.3 3.8 3.3 2.3 1.8 350 400 450 500 300 1.3
DS1337 serial real-time clock 5 of 13 pin description pin name description 1 x1 2 x2 these signals are connections for a standard 32.768khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 6pf. for more information about crystal selection and crystal layout considerations, refer to application note 58: crystal considerations with dallas real- time clocks . an external 32.768khz oscillator can also drive the DS1337. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is floated. 3 inta interrupt output. when enabled, inta is asserted low when the time/day/date matches the values set in the alarm registers. this pin is an open-drain output and requires an external pullup resistor. 4 gnd dc power is provided to the device on these pins. 5 sda serial data input/output. sda is the input/output pin for the 2-wire serial interface. the sda pin is open-drain output and requires an external pullup resistor. 6 scl serial clock input. scl is used to synchronize data movement on the serial interface. 7 sqw/ intb square-wave/interrupt output. programmable square-wave or interrupt output signal. it is an open-drain output and requires an external pullup resistor. 8 v cc dc power is provided to the device on these pins. figure 1. recommended layout for crystal
DS1337 serial real-time clock 6 of 13 figure 2. timing diagram operation the block diagram in figure 3 shows the main elements of the DS1337. as shown, communications to and from the DS1337 occur serially over a 2-wire, bidirectional bus. the DS1337 operates as a slave device on the serial bus. access is obtained by implementing a start condition and providing a device identification code, followed by data. subsequent registers can be accessed sequentially until a stop condition is executed. figure 3. block diagram
DS1337 serial real-time clock 7 of 13 clock accuracy the accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. crystal frequency drift caused by temperature shifts creates additional error. external circuit noise coupled into the oscillator circuit can result in the clock running fast. refer to application note 58: crystal considerations with dallas real-time clocks for detailed information. address map the address map for the registers of the DS1337 is shown in table 1. during a multibyte access, when the address pointer reaches the end of the register space (0fh) it wraps around to location 00h. on a 2-wire start, stop, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. the time information is read from these secondary registers, while the clock may continue to run. this eliminates the need to re-read the registers in case of an update of the main registers during a read. table 1. timekeeper registers address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h 0 10 seconds seconds seconds 00-59 01h 0 10 minutes minutes minutes 00-59 am/pm 02h 0 12/24 10hr 10hr hour hours 1-12 +am/pm 00-23 03h 0 0 0 0 0 day day 1-7 04h 0 0 10 date date date 00-31 05h century 0 0 10 mo month month/ century 01-12 + century 06h 10 year year year 00-99 07h a1m1 10 seconds seconds alarm 1 seconds 00-59 08h a1m2 10 minutes minutes alarm 1 minutes 00-59 am/pm 09h a1m3 12/24 10hr 10hr hour alarm 1 hours 1-12 + am/pm 00-23 day alarm 1 day 1-7 0ah a1m4 dy/dt 10 date date alarm 1 date 1-31 0bh a2m2 10 minutes minutes alarm 2 minutes 00-59 am/pm 0ch a2m3 12/24 10hr 10hr hour alarm 2 hours 1-12 + am/pm 00-23 day alarm 2 day 1-7 0dh a2m4 dy/dt 10 date date alarm 2 date 1-31 0eh eosc 0 0 rs2 rs1 intcn a2ie a1ie control 0fh osf 0 0 0 0 0 a2f a1f status note: unless otherwise specified, the state of the registers is not defined when power is first applied or v cc falls below the v osc .
DS1337 serial real-time clock 8 of 13 clock and calendar the time and calendar information is obtained by reading the appropriate register bytes. the rtc registers are illustrated in table 1. the time and calendar are set or initialized by writing the appropriate register bytes. the contents of the time and calendar registers are in the binary-coded decimal (bcd) format. the day-of-week register increments at midnight. values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on.). illogical time and date entries result in undefined operation. when reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. when reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop and when the register pointer rolls over to zero. the countdown chain is reset whenever the seconds register is written. write transfers occur on the acknowle dge pulse from the device. to avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second. the 1hz square-wave output, if enable, transitions high 500ms after the seconds data transfer, provided the oscillator is already running. the DS1337 can be run in either 12-hour or 24-hour mode. bit 6 of the hours register is defined as the 12- or 24- hour mode-select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20?23 hours). the century bit (bit 7 of the month register) is toggled when the years register overflows from 99?00. alarms the DS1337 contains two time-of-day/date alarms. alarm 1 can be set by writing to registers 07h?0ah. alarm 2 can be set by writing to registers 0bh?0dh. the alarms can be programmed (by the intcn bit of the control register) to operate in two different modes?each alarm can drive its own separate interrupt output or both alarms can drive a common interrupt output. bit 7 of each of the time-of-day/date alarm registers are mask bits (table 2). when all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h?06h match the values stored in the time-of-day/date alarm registers. the alarms can also be programmed to repeat every second, minute, hour, day, or date. table 2 shows the possible settings. configurations not listed in the table result in illogical operation. the dy/dt bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0?5 of that register reflects the day of the week or the date of the month. if dy/dt is written to logic 0, the alarm is the result of a match with date of the month. if dy/dt is written to logic 1, the alarm is the result of a match with day of the week. when the rtc register values match alarm register settings, the corresponding alarm flag (a1f or a2f) bit is set to logic 1. if the corresponding alarm interrupt enable (a1ie or a2ie) is also set to logic 1, the alarm condition activates one of the interrupt output ( inta or sqw/ intb ) signals. the match is tested on the once-per-second update of the time and date registers.
DS1337 serial real-time clock 9 of 13 table 2. alarm mask bits alarm 1 register mask bits (bit 7) dy/dt a1m4 a1m3 a1m2 a1m1 alarm rate x 1 1 1 1 alarm once per second x 1 1 1 0 alarm when seconds match x 1 1 0 0 alarm when minutes and seconds match x 1 0 0 0 alarm when hours, minutes, and seconds match 0 0 0 0 0 alarm when date, hours, minutes, and seconds match 1 0 0 0 0 alarm when day, hours, minutes, and seconds match alarm 2 register mask bits (bit 7) dy/dt a2m4 a2m3 a2m2 alarm rate x 1 1 1 alarm once per minute (00 seconds of every minute) x 1 1 0 alarm when minutes match x 1 0 0 alarm when hours and minutes match 0 0 0 0 alarm when date, hours, and minutes match 1 0 0 0 alarm when day, hours, and minutes match special purpose registers the DS1337 has two additional registers (control and status) that control the rtc, alarms, and square-wave output. control register (0eh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc 0 0 rs2 rs1 intcn a2ie a1ie eosc , enable oscillator. this bit when set to logic 0 starts the oscillator. when this bit is set to logic 1, the oscillator is stopped. this bit is enabled (logic 0) when power is first applied. rs2 and rs1, rate select. these bits control the frequency of the square-wave output when the square wave has been enabled. table 3 shows the square-wave frequencies that can be selected with the rs bits. these bits are both set to logic 1 (32khz) when power is first applied. table 3. square-wave output frequency rs2 rs1 square-wave output frequency 0 0 1hz 0 1 4.096khz 1 0 8.192khz 1 1 32.768khz intcn, interrupt control. this bit controls the relationship between the two alarms and the interrupt output pins. when the intcn bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers l activates the inta pin (provided that the alarm is enabled) and a match between the timekeeping registers and the alarm 2 registers activates the sqw/ intb pin (provided that the alarm is enabled). when the intcn bit is set to logic 0, a match between the timekeeping registers and either alarm 1 or alarm 2 registers activates the inta pin
DS1337 serial real-time clock 10 of 13 (provided that the alarms are enabled). in this configuration, a square wave is output on the sqw/ intb pin. this bit is set to logic 0 when power is first applied. a1ie, alarm 1 interrupt enable. when set to logic 1, this bit permits the alarm 1 flag (a1f) bit in the status register to assert inta . when the a1ie bit is set to logic 0, the a1f bit does not initiate the inta signal. the a1ie bit is disabled (logic 0) when power is first applied. a2ie, alarm 2 interrupt enable. when set to logic 1, this bit permits the alarm 2 flag (a2f) bit in the status register to assert inta (when intcn = 0) or to assert sqw/ intb (when intcn = 1). when the a2ie bit is set to logic 0, the a2f bit does not initiate an interrupt signal. the a2ie bit is disabled (logic 0) when power is first applied. status register (0fh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 osf 0 0 0 0 0 a2f a1f osf, oscillator stop flag. a logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and calendar data. this bit is set to logic 1 anytime that the oscillator stops. the following are examples of conditions that can cause the osf bit to be set: 1) the first time power is applied. 2) the voltage present on v cc is insufficient to support oscillation. 3) the eosc bit is turned off. 4) external influences on the crystal (e.g., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0. a1f, alarm 1 flag. a logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. if the a1ie bit is also logic 1, the inta pin goes low. a1f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. a2f, alarm 2 flag. a logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. this flag can be used to generate an interrupt on either inta or sqw / intb depending on the status of the intcn bit in the control register. if the intcn bit is set to logic 0 and a2f is at logic 1 (and a2ie bit is also logic 1), the inta pin goes low. if the intcn bit is set to logic 1 and a2f is logic 1 (and a2ie bit is also logic 1), the sqw/ intb pin goes low. a2f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged.
DS1337 serial real-time clock 11 of 13 2-wire serial data bus the DS1337 supports a bidirectional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are referred to as slaves. a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions must control the bus. the DS1337 operates as a slave on the 2-wire bus. within the bus specifications a standard mode (100khz maximum clock rate) and a fast mode (400khz maximum clock rate) are defined. the DS1337 works in both modes. connections to the bus are made through the open-drain i/o lines sda and scl. the following bus protocol has been defined (figure 4): data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions are not limited, and are determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition.
DS1337 serial real-time clock 12 of 13 figure 4. data transfer on 2-wire serial bus depending upon the state of the r/ w bit, two types of data transfer are possible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data is transferred with the most significant bit (msb) first. 2) data transfer from a slave transmitter to a master receiver. the master transmits the first byte (the slave address). the slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. data is transferred with the most significant bit (msb) first. the DS1337 can operate in the following two modes: 1) slave receiver mode (write mode): serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit (figure 5). the slave address byte is the first byte received after the master generates the start condition. the slave address byte contains the 7-bit DS1337 address, which is 1101000, followed by the direction bit (r/ w ), which, for a write, is 0. after receiving and decoding the slave address byte the device outputs an acknowledge on the sda line. after the DS1337 acknowledges the slave address + write bit, the master transmits a word address to the DS1337. this sets the register pointer on the DS1337. the master may then transmit 0 or more bytes of data, with the DS1337 acknowledging each byte received. the master generates a stop condition to terminate the data write. 2) slave transmitter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by the DS1337 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer (figure 6). the slave address byte is the first byte received after the master generates a start condition. the slave address byte contains the 7-bit ds1 337 address, which is 1101000, followed by the direction bit (r/ w ), which, for a read, is 1. after receiving and decoding the slave address byte the device outputs an acknowledge on the sda line. the DS1337 then begins to transmit data starting with the register address pointed to by the register pointer. if the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. the DS1337 must receive a ?not acknowledge? to end a read.
DS1337 serial real-time clock maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa 13 of 13 figure 5. data write?slave receiver mode figure 6. data read?slave transmitter mode chip information transistor count: 10,950 process: cmos package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .

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